張耀仁
張老師與他的科技英文與科普傳播 Technical English for Engineering Students Using Claude
星期三, 3月 11, 2026
Analog IC Design (OP741, diff pair, Placement & Routing)
BJT Differential Pair
schematic
Quadratic Placement
ILP+ PathFinder +A* Routing
(
share
)
Plus Pseudo Multi-layer Router
(95% reduction of congestion
md
) no via report
corrected
vias reported
Plus
Symmetry Hard Constraint
(cong=0 match>97%,
artifact
)
neat lohas style
2-stage diff pair
(
share
from very simple diff pair),
block diagram
,
die
,
schematic (B&W)
,
schematic
(color)
corrected
P&R
,
P&R Best
from 1 stage diff pair
tuning
(slides)
Phantom exclusion
artifact
viz
add overlap penalty in placement stage
benchmark
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