Analog IC Design

 

• Overview of Circuit Design
  
  
  
  

IC 

BJT Differential Pair 

schematic

IC Die — A*  with Parameter Optimization by SA 

 share

What is simulated annealing? shown on hyperfunctions comparing to other algorithms

artifact

Quadratic  Placement

ILP+ PathFinder +A* Routing

 (share)

IC Placement & Routing slides

2-stage diff pair (share from very simple diff pair), schematic,  die, Miller Compensation, P&R, P&R+opt compo

OP 741 schematic,  die, P&R