RF PA IC Design Sub 6 GHz

Placement of GaN on SiC 2 stage RF AMP

original , fixed (hardcoded), SA 1, QP, QP+SA (MNA, Small WireLen, non 0 viol.), 

• QP+SA with adaptive cooling schedule (2.55 WireLen, usual. 0 viol.) 
• add congestion penalty in energy (track overflow significantly reduced,  Bench, Overflow Comp, viz, detail viz)

QP+ILP+PrePass (No A* or SA, viol.) comparison with ACS  detail

Slides fit of SA for RF PA Layout

Two-stage cascode Class-AB RF power amplifier targeting 5G n78 (3.5 GHz) in TSMC 28nm RF

Build Sub 6 GHz Power Amplifier Optimizer with Die Synced

Prompts, artifact (Closed-Form), artifact (MNA)

Load-Pull Contours (analytical)

Load-Pull Contours (MNA mixed)

placement (benchmark)

RF Power Amp Driver TSMC N16FFC-RF (one stage)

 (Apple C1 by TSMA N4P is more advanced, no longer apply, not even N3E)

PA Lessons, PA Verified by computing the exact KCL residual at its converged solution, not because of blow up of MNA (share)

PA revision with physical accuracy

what has been changed (shifting not chasing, good)

MNA

Optimizer Apply MNA

what has been changed surface, reality

artifact

artifact (slides)

Optimizer Apply Harmonic (close the loop)

change v9 MNA vs V21 Harmonic

v22

change documentation

visualization (pt A&B by tuning v22 2.2*Vdd, 2*Vdd too tight)

block diagram artifact

RF PA driver with 10 dBm output, not PA itself (realistic spec, not just renaming)

TSMC N16FFC-RF revision (under construction)

TSMC N4P

artifact stacked-FET topologies

artifact

artifact

PA Driver, Real C1 transceiver RF blocks on N4P would be stacked-FET topologies on ~0.9 V core or 1.8 V I/O devices

slides wrap-up