Two-Stage Cascode Class-AB RF Power Amplifier: Placement & Routing

An RF power amplifier is laid out from a few large blocks rather than millions of cells: spiral inductors, wide transistors and capacitors. Where they go sets the wire lengths, the coupling between inductors and the room left for routing, and the job is still mostly done by hand. This page collects browser-based experiments in placing these blocks automatically for the driver of a two-stage cascode class-AB PA. Each version is a self-contained interactive page. The post explains what each one changed and what its benchmarks show.

• Legal placement first. Quadratic placement (QP) alone gives short wires but overlapping blocks. Simulated annealing (SA) removes the overlaps. Ramping its wirelength weight during the run, instead of fixing it, raised the share of fully legal runs from 1 in 10 to 10 in 10, according to a test noted in the code.
• Congestion competes with legality. A congestion penalty in the SA energy cut the estimated routing overflow by about 90%, but fewer runs ended legal: 2 of 20, against 6 of 20 without the penalty. A rerun in Chrome agrees (1 against 7 of 20). At none of eight penalty weights from 0 to 3 did a run bring the peak overflow, with pin density counted, down to the 1.0 that the analysis note calls clean.
• The 28 nm placer stopped too early. The published page ends SA as soon as the layout is legal and its energy small. In 20 seeded runs in Chrome it stopped after 2 to 25 of 180 iterations, and every run ended with a longer wirelength (HPWL) than the hand-placed floorplan: median 96.09 against 71.73. A corrected copy runs the whole schedule. All 20 of its runs end legal and shorter than the hand placement, with a median of 56.83, close to the 54.34 of the Node.js benchmark.
• Scope. Congestion is a grid estimate. No wires are routed, nothing is simulated after placement, and lengths are in layout units.

The circuit · The flow · GaN-on-SiC versions · Congestion vs. legality · The 28 nm placer · Why SA · Limits · Pages and sources

Updated 4 November 2026: five of the linked pages are now corrected copies, checked by running their own code in Chrome, and Section 8 lists them beside the unchanged first versions. The original post of 21 April 2026 is kept at its own address.

1. The circuit and its two dies

Both dies hold the same circuit: a driver stage and a PA stage, each a common-source transistor with a common-gate transistor stacked on top (the cascode). Inductors match the input, the interstage and the output, RF chokes feed bias and supply, and capacitors bypass them. Two versions were built (Table 1).

	GaN-on-SiC die	TSMC 28 nm RF die
Pages	QP to QP + ILP (Section 3)	Placement (Section 5)
Placeable blocks	15: four transistors, three matching inductors, two RF chokes, a source inductor, five capacitors	13: two transistors, six inductors, five capacitors
Fixed pads	7	8
Two-pin nets	28	24
Die	blocks kept within ±4.3 units of the centre	2.8 × 2.3 units, about 1.4 × 1.15 mm at the page's 500 µm per unit
Wirelength	weighted Euclidean length	weighted Manhattan length (HPWL)
Electrical model	S11, S21, noise figure, output power and PAE at 3.5 GHz; from QP + SA on, the S-parameters come from a modified nodal analysis (MNA) solver [3]	none; the page shows a fixed snapshot from a separate circuit optimizer

Table 1. The two dies.

The GaN-on-SiC pages also tune 13 circuit parameters with three optimizers: A* search, gradient descent with momentum, and a Newton-type QP. Placement never feeds back into an electrical score. No layout parasitics enter the models, and the only link between circuit and layout is that the inductance values set the spiral sizes.

Fig. 1. The 28 nm Placement page after a run on 25 April 2026. Spirals are inductors and the two striped blocks are the transistors. The run ended with zero violations and zero estimated overflow at HPWL 91.34, longer than the hand placement because SA stopped early (Section 5). Click any figure for full size.

2. The flow

Every version follows the same plan (Table 2): start from the hand-placed floorplan, pull the blocks together with QP, then push them apart until nothing overlaps.

Stage	What it does	Used in
Start	The hand-placed floorplan. A weak spring ties QP to it, so the result keeps its rough arrangement.	all
QP global placement	Minimizes the quadratic wirelength Σ wij(xi − xj)² [2] plus the spring, solved by Gauss–Seidel. Net weights: RF path 3, ground returns and most bypasses 2, bias and supply 1–1.5.	all
Cell spread	Up to 25 passes that move blocks out of overflowed g-cells.	28 nm
SA legalization [1]	Random moves, accepted by the Metropolis rule, in three cooling cycles with reheats.	all but QP and QP + ILP
Final escape	Tries a 7 × 7 grid of positions for each block still in violation.	28 nm
Congestion report	The g-cell estimate described below.	GaN from annealed λ on; 28 nm

Table 2. Stages of the flow.

SA minimizes an energy with up to four terms:

E = α Σ ov_ij² + β Σ mi_ij² + λ Σ |x_i − x_i^QP|² + γ Σ_g o_g²

ov is how far two footprint circles overlap. mi is how far two inductors sit inside a keep-out of 2.05 (GaN) or 1.75 (28 nm) times the sum of their radii, where their mutual coupling would matter. The λ term holds blocks near their QP positions, and the γ term is the congestion penalty, present only in the congestion-aware versions. A violation is either an overlap or an inductor pair inside the keep-out.

Congestion is estimated on a grid of g-cells, 10 × 11 on the GaN die and 10 × 10 at 28 nm. Each two-pin net of weight w spreads w/√n of routing demand over the n g-cells of its bounding box. A g-cell holds 4.0 tracks inside and 2.5 at the die edge on the GaN die (4.5 and 2.8 at 28 nm). Its overflow o_g is demand minus capacity, where positive. The congestion-aware GaN version also adds half a track per pin of each block.

Metric	Meaning
Violations	Block pairs that overlap, plus inductor pairs inside the keep-out (MI).
WL, HPWL	Weighted sum of net lengths, in layout units.
Overflow tracks	Sum of the positive overflows over all g-cells.
Peak overflow	The largest overflow in any g-cell. The 28 nm page calls a layout routable when it is below 0.01.
Σo²	Sum of squared overflows, the quantity the penalty uses.

Table 3. Metrics used on this page.

3. GaN-on-SiC: six versions

The GaN-on-SiC pages are one 3D viewer that grew step by step (Table 4).

Page	What changed	Reported
original, fixed (hard-coded), SA	Early versions.	No longer online.
QP	QP global placement with a soft push-apart and no legalization.	Short wires, overlapping blocks.
QP + SA	SA legalization with α = 6, β = 4.5 and a fixed λ = 0.18, in three cycles starting at T = 5, 2.5 and 1 and cooling by 0.95 per step. The MNA circuit model arrives here too.	Reheats cut mean violations from 12.9 to 5.5; 1 of 10 runs legal (code comments).
QP + SA, annealed λ	λ ramps as 0.30 p² with run progress p. The temperatures are unchanged. Congestion is reported but not penalized.	10 of 10 runs legal (code comment).
+ congestion penalty	Adds γ Σ o² with γ = 1.8, and demand includes pin density.	Section 4.
QP + ILP + pre-pass	SA removed. Up to 40 sweeps push overlapping pairs apart, and nets are split between metal layers M1 and M2.	10 of 23 violations left in a run of the corrected copy.

Table 4. The GaN-on-SiC versions, in order. Link labels follow the first version of this post.

Two labels from the first version of this post need correcting. The step called “adaptive cooling schedule” leaves the temperature schedule as it was. What it changes is λ, the pull toward the QP solution: near zero early, so SA can move blocks freely while it clears overlaps, and back at full strength as the run ends.

The “ILP” in QP + ILP is not an integer program. The code sorts nets by bounding-box area and gives each one to whichever of the two layers has less bounding-box overlap so far, a greedy rule. The pre-pass then pushes overlapping pairs apart, and since nothing runs after it, any violation left after 40 sweeps stays in the layout. The corrected copy calls the step greedy layer assignment and fits a phone screen; the algorithm is unchanged. In a run of it, the pre-pass took the layout from 23 violations (21 overlaps, 2 MI) to 10 (9 and 1).

4. Congestion against legality

The congestion penalty was tested four ways. A single-run comparison in the analysis note shows what it is for. Overflowed g-cells fell from 16 to 2 of 110, overflow from 15.5 tracks to about 2, and peak overflow from 2.4 to 1.33, while WL rose 17%, from 272.1 to 317.1. The before and after are on two scales, though. The v2 figures come from v2's log, which leaves out pin density, and the v3 figures from v3's log, which counts it. v3's log prints no total and no cell count, and its “2 tracks overflowed” is the peak of 1.33 rounded up.

A 10-seed benchmark at default footprints shows the cost. SA starts from a QP result with 26 violations (21 overlaps, 5 MI) and WL 110.7. With the penalty, no seed ended legal: 1 to 5 violations remained (mean 2.9), and WL ended between 272 and 368 (mean 317). Legalization nearly triples the QP wirelength on this die, and by the pin-density estimate 10 to 21 g-cells still overflow.

The fairest test is a 20-seed comparison with footprints calibrated to one circuit: input, interstage and output inductors of 1.4, 1.8 and 1.3 nH, and transistor widths of 200 and 360 µm. Both variants start from the same QP result and use the same SA schedule (Table 5).

Mean over 20 seeds	Penalty in SA	Report only
Legal runs	2 of 20	6 of 20
Violations: overlaps / MI	1.40 / 0.95	1.15 / 0.15
Overflow tracks, without pin density	1.0	13.9
Peak overflow, without pin density	0.41	2.56
Peak overflow, with pin density	1.83	4.63
WL	305	327
Time per run	18.4 s	5.4 s

Table 5. Calibrated footprints; the better value in each row is in bold. That page labels the penalty v1 and report only v2, while the analysis note calls the version without the penalty v2.

The penalty removes about 93% of the overflow, but it leaves more runs illegal, 18 of 20 against 14 of 20. Most of the extra violations are inductor pairs inside the keep-out. The 17% wirelength cost from the single run did not hold here: with the penalty, WL was 7% lower on average. Without it, 6 of 20 runs ended legal, fewer than the 10 of 10 noted in the code at default footprints.

The corrected congestion dashboard scores both versions on both scales, with 20 seeded runs of each page's own code in Chrome. QUAD PLACE first tunes the circuit, and it settles on the same 1.4, 1.8 and 1.3 nH and 200 and 360 µm as the calibrated comparison, so these runs repeat the test behind Table 5. The means come out close to it: 1 of 20 runs legal with the penalty against 7 of 20 without, peak overflow 0.28 against 2.55 without pin density and 1.78 against 4.59 with it, and WL 306.7 against 330.5. The penalty removes 96% of the overflow as v2 reports it, and 73% with pin density counted.

The first dashboard also plotted a sweep of γ from 0 to 3 that has no source. Measured at eight values, 20 runs each, total overflow falls steeply up to γ = 1 and slowly after it, the peak with pin density levels off near 1.7 to 1.8, and WL comes out shorter than at γ = 0, between 295 and 321, instead of rising. At every γ above 0 only 1 to 6 runs of 20 end legal, against 7 at γ = 0, and none of the 160 runs brings the peak down to the 1.0 that the note calls clean; the lowest is 1.13. With all four of the note's tuning suggestions applied (γ = 2.5, tighter g-cell capacities and longer cooling cycles), the mean peak is still 1.79 and none of the 20 runs ends legal.

5. The 28 nm placer

The Placement page is a rewrite for TSMC 28 nm RF, aimed at 5G band n78 (3.3–3.8 GHz [4]) with the circuit centred at 3.5 GHz; the circuit itself is sized in the companion post on parameter optimization. The page places only: sliders resize the spirals and the PA transistor, but no electrical cost is computed. Its spiral footprints are 55–100 µm in radius, which the code calls in line with published 28 nm spirals; the earlier radii were 3–5 times larger.

The pipeline adds three things to the GaN flow. A cell-spread step runs between QP and SA. The SA temperatures are fractions (0.05, 0.02 and 0.005) of the starting energy E₀, with a random kick at each reheat. A final escape step comes last. λ ramps as 0.06 p², and once three or fewer violations remain, every block may move and the move range grows 1.6 times.

QP and the spread step are deterministic, so every run starts SA from the same layout (Table 6). QP halves the hand-placed wirelength but packs the blocks into a hotspot. The spread step brings the peak overflow down from 5.28 to 1.08 and gives back about half of the gain.

Stage	HPWL	Violations	Peak overflow
Hand-placed start	71.73	3	1.57
After QP	33.49	–	5.28
After cell spread (SA start)	52.20	8	1.08
After SA, published page, Chrome, 20 seeds	76.24–106.81, median 96.09	0 in all 20	below 0.01 in 9
After SA, corrected copy, Chrome, 20 seeds	53.91–66.07, median 56.83	0 in all 20	below 0.01 in 14
After SA, Node.js benchmark, 20 seeds	52.09–73.68, median 54.34	0 in all 20	below 0.01 in 16

Table 6. Where the 28 nm runs go. QP and spread values are from the page log; violations after QP are not logged. The Chrome runs of 4 November 2026 replace Math.random with a seeded generator (seeds 1–20), and all 40 start SA at 52.20. The Node.js replay used its own generator, so its seeds do not match. The screenshot in Fig. 1 (91.34) and two unseeded runs of 3 November (75.73 and 85.58) also came from the published page.

Fig. 2. Final HPWL of the 28 nm placer, one dot per run. Every run of the published page ends above the hand-placed start and every run of the corrected copy below it, near the Node.js benchmark. Hover over a dot for its run.

Why does the published page end longer? After the spread step the SA energy is already small (E₀ = 5.74 in every run), so the first temperature is only 0.29. SA stops as soon as no violations remain and the energy is below 0.05, which in the 20 seeded runs came after 2 to 25 of 180 iterations. By then λ was at most 0.0012, a fiftieth of its final 0.06, so nothing held the blocks near the short-wire layout while SA pushed them apart. Comments in the code expect E₀ of 50 to 200 and a full-length run, but with the smaller footprints that no longer holds.

The corrected Placement copy drops that early stop, so SA always runs its 180 iterations and λ reaches 0.06. All 20 seeds then end legal and shorter than the hand placement, at a median HPWL of 56.83, 21% below it, and 14 of 20 end with peak overflow below 0.01. The copy also corrects the code comment about E₀, drops the labels that name an MNA solver the page does not have, and fits a phone screen.

The benchmark page describes the same pipeline but does not publish its script, and most of its HPWL values sit close to the 52.20 that SA starts from. Its 20 Node.js seeds end near the corrected copy, not the published page, so they show what a full-length run does. The corrected benchmark page keeps those rows, adds the 40 Chrome runs, and gives the median as 54.34; the first version showed 54.66, the upper of the two middle values. Node.js seed 1 (73.68) ends worse than the hand-placed start.

Fig. 3. The 20-seed benchmark page as first published, with its median tile at 54.66.

The first version of the change log describes the 28 nm rewrite with an overlap weight α = 50, β = 20, a temperature tied to footprint size, a linear λ ramp from 0.02 to 0.10, and no move-range boost. The published page has α = 6, β = 4, temperatures tied to E₀, a quadratic ramp to 0.06 and the boost, and the benchmark page also names E₀-tied temperatures and the boost. So the change log lists changes that are not in the published page. It also says the GaN reheat schedule only ever cooled, but the 10-seed traces show the temperature jumping from 0.24 to 2.5 and from 0.12 to 1.0 at the cycle boundaries. The corrected change log checks each of its 21 entries against the code of the two pages (6 match, 3 match in part, 12 do not), lists the settings as the code has them, and adds the stop-rule fix as its newest entry.

6. Why simulated annealing

The slides make the case for SA here. A class-AB PA has about 10 to 15 layout elements, a search space small enough for SA to explore. Its objectives, such as PAE, gain and S11, come from simulation rather than from proxies like overflow. And two inductors that come too close couple, so performance can jump with a small move; SA needs no gradient and copes with such jumps.

The slides propose a two-tier loop, with a quick circuit simulation for every move and EM simulation only for promising layouts. They also name four directions: moves that rotate blocks and turn inductor axes as well as shift them, multi-objective (Pareto) SA, thermal and EM co-optimization, and an open-source RF PA layout optimizer. None of the placers above closes that loop yet. Their cost is wirelength, overlap and congestion, and the electrical scores never see the layout.

7. What these pages do not show

• No routing. The route stage reports the g-cell estimate. No wires are drawn on metal layers, and nothing checks design rules.
• No post-layout simulation. No parasitics are extracted, and inductor coupling enters only as a keep-out distance.
• Few runs. 10 or 20 seeds per setting, each on one circuit configuration. The scripts behind the first benchmark pages are not published. The Chrome runs of 4 November call each page's own code with a seeded random generator, as the corrected pages describe.
• Different setups. The GaN-on-SiC and 28 nm results use different netlists, footprints and estimators, so their numbers do not compare.
• Units. Lengths are layout units. The first congestion dashboard labelled WL in µm and the analysis note calls a g-cell 1 mm wide; neither unit is used here.

8. Pages and sources

GaN-on-SiC die. Placers: QP, QP + SA, QP + SA with annealed λ, congestion penalty, QP + ILP + pre-pass (corrected). Congestion results: 10-seed benchmark, analysis note, dashboard (corrected), calibrated 20-seed comparison. First versions: QP + ILP + pre-pass, dashboard; the first dashboard's subtitle says TSMC 28 nm RF, but its 10 × 11 grid and numbers belong to the GaN-on-SiC die. No longer online: original, fixed (hard-coded), SA, the QP + ILP detail page, and “RDP or not”.

28 nm die. Corrected copies: Placement, change log, 20-seed benchmark. First versions: Placement, change log, 20-seed benchmark. The circuit: Two-stage Cascode Class-AB RF PA driver: parameter optimization.

Background. Slides: SA for RF PA layout, a research note of April 2026. The corrected copies of 4 November 2026 carry “(corrected)” in their titles and say what they change; the first versions are left as they were. The original post of 21 April 2026 keeps all the original links.

[1] S. Kirkpatrick, C. D. Gelatt and M. P. Vecchi, “Optimization by simulated annealing,” Science, vol. 220, no. 4598, pp. 671–680, 1983. doi:10.1126/science.220.4598.671

[2] J. M. Kleinhans, G. Sigl, F. M. Johannes and K. J. Antreich, “GORDIAN: VLSI placement by quadratic programming and slicing optimization,” IEEE TCAD, vol. 10, no. 3, pp. 356–365, 1991. doi:10.1109/43.67789

[3] C.-W. Ho, A. E. Ruehli and P. A. Brennan, “The modified nodal approach to network analysis,” IEEE Trans. Circuits and Systems, vol. 22, no. 6, pp. 504–509, 1975. doi:10.1109/TCS.1975.1084079

[4] 3GPP TS 38.101-1, NR user equipment radio transmission and reception, Part 1: Range 1 standalone. Band n78 is 3300–3800 MHz.