Follow up EX#8

 LNA reality check in simulator, prompt for spec compliance

LNA v3 (closed-form), V3 pathway to tape-out (advanced, ok omitted)

如果提示僅有一次性的張貼，沒有調整與修正，輸出結果簡略缺少

如有演算法有錯，請回顧上週作業

建議使用老師提供提示，逐一嘗試，只是問題貼上就期待答案正確，這是緣木求魚，不是很會用 AI的方式。

嘗試錯誤會遭遇一些困難，但這個才會有學習，試看看這個人機協作如何形成，變成你帶得走的能力。

用 svg 格式畫電路圖非常消耗 AI 算力

因為要計算每個元件的位置與大小與風格

電路圖不完全正確

可能原因就是你的試用版無法給予足夠的算力

不過沒關係

介面很完整，需要顯示的參數gain, s21, s11, s22, freq responses, 齊備⋯⋯

主要的問題是功能，內部運算，演算法都是假的，像是展示用的手機，外表接近真品，但不能打電話上網。

可能原因

1. 免費版的AI ，因為算力有限，只做外皮 UI

2. 提示沒有步驟，把所有的要求寫在一起，致使AI 算力超越單次回應的上限，因此所有預算都用在外表，內部功能是空虛的。

如果Claude免費版不夠用

前面推理可以用 aistudio 

後段視覺化再用 Claude

EX#8 LNA (Low Noise Amplifier)

 建議工具

使用 Claude Sonnet 4.6 推理模式(手動切換，免費用戶額定時間內只能使用三次)

使用 ChatGPT 5 推理模式(自動切換)

使用 Gemini 3.0 Pro 免費額度最高 1M tokens (永遠推理模式)

使用 Grok 4 推理模式(自動切換)

---

How to publish a Claude artifact

How to share a ChatGPT link

How to share a Grok link

How to share Gemini Link

作業繳交規範

guidelines

Content share 作業繳交格式

• share only link, pure text, markdown (md)
• no attachments accepted, no html, screen dump, or png
• non-compliant homework will be rejected and returned to you

課堂練習 

Deadline: This Saturday at 23:59

Send all the share links to  me chang212@gmail.com by email with subject EX#8  [your id, your name]

 1.  Study Apple iPhone Architecture & Design Guides

(a) make LNA schematic (TSMC N7 製程的完整設計流程，包含完整元件表、元件值推導公式、die 面積估算) LNA=Low Noise Amplifier

(b) make LNA Die

share

(c) Build LNA Optimizer (SMITH Chart, S-parameters, Frequency Response), Merit of Figure (share)

share 1, share 2, share 3

(d) Build a Simplified (closed-form) LNA optimizer (with GD, A*) on Die, 3.5 GHz LNA TSMC N7. 

Note: LNA Optimizer with Die and sliders Synced  (Optimizer  with NM method added)

Prompts, Cont. Prompts (same as last)

(e) (選作) 需要付費版算力，免費版可能無法完成

Build an MNA model (Modified Nodal Analysis, as used in Cadence Spectre engine)  to optimize. Must verify your results to meet spec and parameters have to be realistic.

Want to get these figures, see the Claude share. (Opus 4.6)

Hints: all the prompts used in the conversation, prompts lined up

Supplemental

1. Explain Smith Chart

Electronics Example 8: Analog IC Design (OP741, diff pair, Parameter Optimization)

 BJT Differential Pair 

schematic with parameter optimizer

optimizer corrected

Common issues

2-stage diff pair (share from very simple diff pair), block diagram,  die, 

schematic (B&W), schematic (color)

corrected

Miller Compensation: miller slides,  slides detailed, 

Miller Compensation

OP 741

 schematic,  die, P&R

modern global placement: ePlace vs. RePlAce

 ePlace vs. RePlAce

compare ePlace with RePlAce animation

cell inflation

macros added (cell_w = 0.15)

final numbers

artifact

slides: modern global placement

Two-stage Cascode Class-AB RF PA driver: parameter optimization

  Two-stage Cascode Class-AB RF PA Driver targeting 5G n78 (3.5 GHz) in TSMC 28nm RF CMOS

Difference between this html TSMC 28nm RF CMOS and TSMC N3E jsx closed-form 

SMITH Chart,  Explain Smith Chart, S-parameters (read it if you are not familiar with these concepts.)

Build Sub 6 GHz Power Amplifier Optimizer with Die Synced

share, artifact (Closed-Form)

benchmark

impedance match

2-stage RF PA driver 

paper, level of physics

artifact

Optimizer with Load-Pull Contours (analytical)

Optimizer with Load-Pull Contours (MNA mixed) share

Newton DC+ Multi-Harmonic Balance log

the design (2 by 2, 2 by 2 re-styled, Thermal model), log, ∠Γ_3f₀ phase (deg) · open=0, -170 deg

margin-first build, Thermal model

design choices

ASAP7 json1 json2 json3 share, benchmark prompt recipes

ASAP7 Class-F (auto-load)

dual attractors

basin transitions

GaN, "Calibrated for 0.25 µm GaN-on-SiC RF process (Wolfspeed G2 / WIN NP25 class)" for base station

artifact (topology change, single device)

Two-stage Cascode Class-AB RF power amplifier: Placement & Routing

Placement of GaN on SiC 2 stage RF AMP

original , fixed (hardcoded), SA 1, QP, QP+SA (MNA, Small WireLen, non 0 viol.), 

• QP+SA with adaptive cooling schedule (2.55 WireLen, usual. 0 viol.) 
• add congestion penalty in energy (track overflow significantly reduced,  Bench, Overflow Comp, viz, detail viz)

QP+ILP+PrePass (No A* or SA, viol.) comparison with ACS  detail

Slides fit of SA for RF PA Layout

 Two-stage Cascode Class-AB RF power amplifier targeting 5G n78 (3.5 GHz) in TSMC 28nm RF

Placement (refinement of add congestion penalty in energy)

change log

Placement (refinement of add congestion penalty in energy)

change log

benchmark

pipeline of placement process (comparison with ePlace, RePlAce)

EM-Aware

EM-Aware Placer

EM × λ-Aware Placer (dev log) v2

Routing added

EM × λ-Aware Placer + Pathfinder  v3

remove phantoms and reweigh EM viol leveraging router/pathfinder v3+, roadmap

benchmark (phantoms-exit)

catastrophic 

v4 with MT, benchmark, roadmap

RF Power Amp Driver TSMC N3E-RF

 RF Power Amp Driver TSMC N3E-RF (one stage) 

 (note: Apple C1 by TSMA N4P )

PA Lessons, PA Verified by computing the exact KCL residual at its converged solution, not because of blow up of MNA

SMITH Chart,  Explain Smith Chart

Design Work Flow

Design matching network

artifact slides

Angelov model  (share)

PA revision with physical accuracy

what has been changed (shifting not chasing, good)

MNA

Optimizer Apply MNA

what has been changed surface, reality

artifact

artifact 

Optimizer Apply Harmonic (close the loop)

change v9 MNA vs V21 Harmonic

Doherty architecture

Gemini 3.0 Pro

Opus 4.7 Adaptive

Apple C1 Doherty

Apple C1 / n78 handset Doherty PA 的真實規格範圍

PAPR、Back-off、與 Doherty 的存在理由(share)

v22

change documentation

visualization (pt A&B by tuning v22 2.2*Vdd, 2*Vdd too tight)

learning roadmap

v23 self-heating loop

v24 MNA for S parameters

v25* IMN+OMN, brute force+ NM Opti.

v26* IMN+OMN, brute force+ CMA-ES (v23-v26 change log)

block diagram artifact

RF PA driver with 10 dBm output (not PA itself) (code, artifact, realistic spec, not just renaming)

Vdd @N3E nominally 0.75, max 0.8 V. The simulator default 3.3 V, too high

fix 1. thick ox 1.8v N4P single device (when cascode, v_mid approximation) No newton, No HB

fix 2. thick ox 1.8v N4P cascode (option single also works.) HB, Newton compute -- educational, no novelty

PA Driver, C1 transceiver RF blocks on N4P

 TSMC N4P slides wrap-up

artifact stacked-FET topologies

corrected

artifact

artifact

PA Driver, Real C1 transceiver RF blocks on N4P would be stacked-FET topologies on ~0.9 V core or 1.8 V I/O devices

Gaps in Physics

physically eqiv to

fix 2. thick ox 1.8v N4P cascode (option single also works.) HB, Newton compute in RF Power Amp Driver TSMC N3E-RF