星期三, 5月 06, 2026

Follow up EX#9

To speed up the process, you may want to use Claude cowork to run the batch using Python which Claude will make one for you automatically.

1. BJT Diff Pair

Interesting result — the MNA contradicts the React optimizer. Let me sweep mirror mismatch to show what's going on:The MNA disagrees with the optimizer by oo dB. Here's why:

                     analytic (React)       MNA (full nodal solve)
  |Ad|                       1286.7                  1293.4
  |Acm|                   3.50×10⁻⁵               1.70×10⁻³
  CMRR (dB)                   151.30                  117.65
                                              ← 34 dB lower

Root cause: PNP mirror β-error, which the React formula completely omits.

The textbook expression Acm = 1/(2·gm·R_tail) assumes a perfect mirror — gain exactly 1. Real PNP mirrors lose 2/(β+2) of the reference current to base currents. With β_p ≈ 106:

δ_β = 2/(β+2) = 1.84%
Predicted Acm from β-loss: δ·Rout/(2·R_tail) = 1.66×10⁻³
Observed Acm (MNA):                            1.70×10⁻³
→ β-error explains 98.1% of the actual CM gain

The tail-impedance term (3.5×10⁻⁵) is real but it's the floor, not the dominant contributor. The mirror β-error is 48× larger and sets the actual CMRR.

Mirror Is-mismatch sweep confirms the mechanism — there's an asymmetric peak where Is mismatch cancels β-loss:

  ΔIs/Is     CMRR
   −5%      106.5
   −2%      111.5
    0%      117.7   ← matched (β-loss alone)
   +1%      123.8
   +2%      155.7   ← cancellation peak (Δ_Is exactly = δ_β)
   +3%      123.5
   +5%      114.2

That sharp 156 dB peak at +1.84% is real but useless — it's a single bias-trim point. Process variation puts every die somewhere else on the curve.

Monte Carlo with realistic process σ (0.5% Is, 1% β):

  CMRR mean   = 119.4 dB
  CMRR median = 117.5 dB
  CMRR p10    = 112.8 dB
  CMRR p90    = 127.4 dB
  CMRR std    =   7.3 dB

Verdict on the optimizer's CMRR numbers: systematically optimistic by ~33 dB. The 117–120 dB result is in line with what real BJT diff pairs with active loads achieve (LM394: 120 dB typ; MAT02: 124 dB typ — both trimmed). The optimizer's 151 dB was the textbook ceiling for an idealized topology, not what the topology actually delivers.

Two-line fix for the React calcPerf:

const deltaBeta = 2 / (bp + 2);                          // mirror β-loss
const Acm_beta  = deltaBeta * Rout / (2 * RoTail);
const AcmTotal  = Math.hypot(AcmLin, Acm_beta);          // RMS combine
const CMRR      = 20 * Math.log10(AdLin / AcmTotal);

That alone pulls the reported CMRR from 151 to ~118 dB and aligns it with what an MNA — or a real chip — would show.


EX#9 Benchmark IC Design Quality

  課堂練習 

Deadline: This Saturday at 23:59

Send all the share links to  me chang212@gmail.com by email with subject EX#9 [your id, your name]


Part 1

Use Claude CoWork or Claude.ai/aistudio to benchmark  BJT Differential Pair 

 1. Experiments with 30 seeds


schematic with parameter optimizer


Hint: prompts for CoWork
Prompts for Claude Chat


Part 2

1. Benchmark the three algorithms (GD, NM, A*) and their cascades (one designed by you and the other design by AI )

  • For the five methods, each runs with 10 seeds
  • Tabulate Gain, Pout, PAE, OP1dB, S₁₁ (5 methods = 5 tables, each table with 5 metrics × 10 seeds = 40 cells).
  • Visualize all of your data

Two-stage Cascode Class-AB RF PA Driver targeting 5G n78 (3.5 GHz) in TSMC 28nm RF

Build Sub 6 GHz Power Amplifier Optimizer with Die Synced
shareartifact (Closed-Form)


星期三, 4月 29, 2026

Follow up EX#8

 LNA reality check in simulator, prompt for spec compliance

LNA v3 (closed-form), V3 pathway to tape-out (advanced, ok omitted)

如果提示僅有一次性的張貼,沒有調整與修正,輸出結果簡略缺少
如有演算法有錯,請回顧上週作業
建議使用老師提供提示,逐一嘗試,只是問題貼上就期待答案正確,這是緣木求魚,不是很會用 AI的方式。
嘗試錯誤會遭遇一些困難,但這個才會有學習,試看看這個人機協作如何形成,變成你帶得走的能力。

用 svg 格式畫電路圖非常消耗 AI 算力
因為要計算每個元件的位置與大小與風格

電路圖不完全正確
可能原因就是你的試用版無法給予足夠的算力
不過沒關係

介面很完整,需要顯示的參數gain, s21, s11, s22, freq responses, 齊備⋯⋯
主要的問題是功能,內部運算,演算法都是假的,像是展示用的手機,外表接近真品,但不能打電話上網。

可能原因
1. 免費版的AI ,因為算力有限,只做外皮 UI
2. 提示沒有步驟,把所有的要求寫在一起,致使AI 算力超越單次回應的上限,因此所有預算都用在外表,內部功能是空虛的。

如果Claude免費版不夠用
前面推理可以用 aistudio 
後段視覺化再用 Claude

EX#8 LNA (Low Noise Amplifier)

 建議工具

使用 Claude Sonnet 4.6 推理模式(手動切換,免費用戶額定時間內只能使用三次)

使用 ChatGPT 5 推理模式(自動切換)

使用 Gemini 3.0 Pro 免費額度最高 1M tokens (永遠推理模式)

使用 Grok 4 推理模式(自動切換)



How to publish a Claude artifact

How to share a ChatGPT link

How to share a Grok link

How to share Gemini Link



作業繳交規範

guidelines


Content share 作業繳交格式

  • share only link, pure text, markdown (md)
  • no attachments accepted, no html, screen dump, or png
  • non-compliant homework will be rejected and returned to you


課堂練習 

Deadline: This Saturday at 23:59

Send all the share links to  me chang212@gmail.com by email with subject EX#8  [your id, your name]


 1.  Study Apple iPhone Architecture & Design Guides

(a) make LNA schematic (TSMC N7 製程的完整設計流程,包含完整元件表、元件值推導公式、die 面積估算) LNA=Low Noise Amplifier


(b) make LNA Die


(c) Build LNA Optimizer (SMITH ChartS-parameters, Frequency Response), Merit of Figure (share)






(d) Build a Simplified (closed-form) LNA optimizer (with GD, A*) on Die, 3.5 GHz LNA TSMC N7. 

Note: LNA Optimizer with Die and sliders Synced  (Optimizer  with NM method added)



PromptsCont. Prompts (same as last)

(e) (選作) 需要付費版算力,免費版可能無法完成

Build an MNA model (Modified Nodal Analysis, as used in Cadence Spectre engine)  to optimize. Must verify your results to meet spec and parameters have to be realistic.




Want to get these figures, see the Claude share. (Opus 4.6)

Hints: all the prompts used in the conversationprompts lined up



Supplemental

1. Explain Smith Chart


星期二, 4月 21, 2026

Two-stage Cascode Class-AB RF power amplifier: Placement & Routing

Placement of GaN on SiC 2 stage RF AMP

original , fixed (hardcoded), SA 1QPQP+SA (MNA, Small WireLen, non 0 viol.), 

QP+ILP+PrePass (No A* or SA, viol.) comparison with ACS  detail

Slides fit of SA for RF PA Layout


 Two-stage Cascode Class-AB RF power amplifier targeting 5G n78 (3.5 GHz) in TSMC 28nm RF

pipeline of placement process (comparison with ePlace, RePlAce)



EM-Aware



Routing added


benchmark (phantoms-exit)

catastrophic 



v4 with MT, benchmark, roadmap

RF Power Amp Driver TSMC N3E-RF

 RF Power Amp Driver TSMC N3E-RF (one stage) 

 (note: Apple C1 by TSMA N4P )


PA Lessons, PA Verified by computing the exact KCL residual at its converged solution, not because of blow up of MNA


SMITH Chart,  Explain Smith Chart


Design Work Flow




Design matching network
artifact slides






what has been changed (shifting not chasing, good)




MNA
Optimizer Apply MNA
what has been changed surfacereality





Optimizer Apply Harmonic (close the loop)
change v9 MNA vs V21 Harmonic






Gemini 3.0 Pro


Apple C1 Doherty
Opus 4.7 Adaptive









visualization (pt A&B by tuning v22 2.2*Vdd, 2*Vdd too tight)


v23 self-heating loop
v24 MNA for S parameters
v25* IMN+OMN, brute force+ NM Opti.
v26* IMN+OMN, brute force+ CMA-ES (v23-v26 change log)

block diagram artifact


RF PA driver with 10 dBm output (not PA itself) (code, artifact, realistic spec, not just renaming)



Vdd @N3E nominally 0.75, max 0.8 V. The simulator default 3.3 V, too high

fix 1. thick ox 1.8v N4P single device (when cacode, v_mid approximation) No newton, No HB
fix 2. thick ox 1.8v N4P cascode (option single also works.) HB, Newton compute



PA Driver, C1 transceiver RF blocks on N4P

 TSMC N4P slides wrap-up


artifact stacked-FET topologies









PA Driver, Real C1 transceiver RF blocks on N4P would be stacked-FET topologies on ~0.9 V core or 1.8 V I/O devices



physically eqiv to
fix 2. thick ox 1.8v N4P cascode (option single also works.) HB, Newton compute in RF Power Amp Driver TSMC N3E-RF