EX#8 Computer Vision

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Deadline:  Saturday at 23:59 (one more week on 11/14)

Send all the share links to  me chang212@gmail.com by email with subject EX#8 [your id, your name]

二選一

1. 針對以下一個意外事件，模擬一個預防措施

Quoting one chain from a list and adding “animate it” gave a page that plays the chain step by step, from the hazard to the injury. Table 3 lists the nine chains. Six have pages of their own; the other three, and two more TV tip-overs, are inside the shared chats.

Chain
Wet floor and soap → slip → strike the tub or a cabinet	家中浴室, with its 危害鏈 diagram
Climb the sofa → stand on its back → reach the window	客廳窗戶攀爬危害鏈 (in the chat)
Shelving unit → climbing → tip-over	Shelving Unit
TV and stand → climbing or pulling → tip-over → crushing	TV & Entertainment Center (chat A); B and C in their chats
Floor fan → fingers in the blades	Moving Parts
Curtain cord → caught around the neck	模擬纏繞
Glass coffee table → fall → head strikes a corner	模擬尖銳桌角

Window -Furniture anchors                               攀爬窗邊墜落

2. 選擇以下一個場景，製作一個環境安全檢測系統 Photos: photo gallery. 

• Scenes: 1 3D Safety Assessment · 2 Campus Safety Assessment 3D · 3 Walkway Hazard Survey · 4 Fractal Forest Safety  · 5 跑道三維碎形場景重建 · 6 3D Plaza Scene with Fractal Nature.

EX#7 Optimize circuits

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Deadline: This Saturday at 23:59

Send all the share links to  me chang212@gmail.com by email with subject EX#7 [your id, your name]

Design a Two-Stage BJT Amplifier according to goals specified  (Parameters to optimize RE1, RC1. RE2. RC2) 

EX#6 Mathematical Optimization

Deadline: 週六 23:59（Saturday at 23:59）

Send all the share links to me chang212@gmail.com by email with subject EX#6 [your id, your name]

進入 EX#6 Mathematical Optimization（interactive）

EX#5 Placement and Routing for OP Amp IC

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Deadline:  Saturday at 23:59

Send all the share links to  me chang212@gmail.com by email with subject EX#5 [your id, your name]

To share your work, refer to the following.

How to publish a Claude artifact

How to share a ChatGPT link

How to share Gemini Link

P&R for OP 741.

schematic 

「用 Claude 做類比 IC 設計」系列頁面12345678910111213141516171819模型：NPN β 200、V_A 100 V；橫向 PNP β 50、V_A 50 V、τ_F 30 ns；V_T 25.85 mV、V_BE 0.65 V回到部落格文章

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Handout: Analog IC Design (OP741, diff pair, Placement & Routing)

1. Place and route the IC OP741

   Layout targets

   These targets apply only to the bonus phases. They are measured on the extended netlist from Phase 2 and averaged over the same 10 seeds. Phase 1 is graded on reproduction and ablation alone. "Phase 1 baseline" means your own reproduction of the handout on that netlist before any change.

   Metric	Target	Handout baseline
   Routing convergence	10/10 seeds with 0 shared cells	10/10 (core only)
   PathFinder rounds	mean ≤ 4	2–4
   Input path-length match	mean ≥ 95%, worst seed ≥ 90%	95.0% (seed 137)
   Input-net resistance mismatch, vias included	≤ 2%	—
   Coupling, each input net to VOUT	≤ 2 fF, and Vin+ within 10% of Vin−	—
   Output-stage centroid	within 1 cell of x = 40	—
   Output stage to input quad	≥ 40% of die height apart	—
   Thermal offset estimate (2 °C/mm model)	≤ 50 µV	—
   Wirelength + vias	≤ 1.15× Phase 1 baseline	434 + 24 (seed 137)
   Runtime per seed	≤ 2× Phase 1 baseline	—

   A team that misses a target but explains the trade-off with data can still earn most of the credit.

   Project tasks

   1. Run the handout's engine on the single-stage diff pair and the two-stage core. Reproduce every row of the handout's Table 1 and the two-stage result.
   2. Remove one part at a time and measure the effect on convergence, rounds, match, wirelength and vias:
      • SimPL-style anchors off
      • RUDY congestion stage off (λ = 0)
      • halo m = 0, 1 and 2
      • nets routed as trees vs split into two-pin connections
      • one layer vs three layers
   3. Record runtime per seed. This is the Phase 1 baseline used in the targets.

   Checkpoint: a reproduction table next to the handout's numbers, plus one ablation table. Explain any number that differs from the handout by more than 10%.

   
   
   
   
   Placer & Router for OP 741 (sample) 註：元件尺寸不對，可以使用Spice 計算驗證真正的幾何
   
   

   2.  Experiment with 10 seeds for the circuit in Problem 1

   Measure success, congestion, wirelength, overlap pairs (before/after), Vin length match. 
   
   
   
   

   
   

   

   benchmark

   
   

PnR for OP Amp, Placement and Routing

 (sonnet 5.5 Medium)

 

Here are your prompts from this session, in order:

1. [schematic image attached] "IC PnR, on a die"
2. "device level"
3. "components on a die"
4. "3d die"
5. "with routing"
6. "extract netlist from schematic" (with the schematic image attached again)
7. "The next step is a Python router (e.g. a grid maze router on M1/M2) that produces these wires automatically from the netlist. I can write it if you want. I'd need your netlist and layer pitches to make it real. do it"
8. "routed svg in png"
9. "show all prompts this session"

Prompt 7 quotes my earlier offer, followed by your "do it".

(Opus 5.5 Max)

Two-stage BJT op-amp on a die

Also your six prompts in order, in Taipei time.

PCB trace route

 You may want to try a more industrial level approach since you already handle it very well at the basic level.

Compare your PCB trace route with the following. Look at the angles and widths to reduce electromigration and Electromagnetic Compatibility.

PCB for Differential Pairs

Debug LLM-written PnR codes for PCB Design 

consider current density

https://claude.ai/artifact/T6KgJqxfHcVp1nzdFcodRc

EX#4

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Deadline:  Saturday at 23:59

Send all the share links to  me chang212@gmail.com by email with subject EX#4 [your id, your name]

To share your work, refer to the following.

How to publish a Claude artifact

How to share a ChatGPT link

How to share Gemini Link

1. Optimize trace routing on PCB given the schematic of Differential Pair Circuit  

schematic 

sample trace routing, share (schematic)

Steps

Do trace routing ( 參考 share, share 2, share 3)

2. 續上題，使用鑽孔路徑演算法進行PCB 鑽孔

3. Depict 3D PCB 

Hint: worked out example PCB for Differential Pairs

(Bonus) 4. 接上題，Run spice simulation using NGSpice 4.6, LTSpice, or HSpice ...

結果必須包含 log、版本資訊、結果輸出

Hint: Run NGSpice in Claude Sandbox

(Bonus) 5. Build a MP4 for the process of a PCB Design (materials for your production)