Follow up EX#8

 LNA reality check in simulator, prompt for spec compliance

 

LNA v3 (closed-form), V3 pathway to tape-out (advanced, ok omitted)

用 svg 格式畫電路圖非常消耗 AI 算力

因為要計算每個元件的位置與大小與風格

當然少不了要正確

目前你的電路圖不完全正確

可能原因就是你的試用版無法給予足夠的算力

不過沒關係

如果Claude免費版不夠用

前面推理可以用 aistudio 

後段視覺化再用 Claude

EX#8 LNA (Low Noise Amplifier)

 建議工具

使用 Claude Sonnet 4.6 推理模式(手動切換，免費用戶額定時間內只能使用三次)

使用 ChatGPT 5 推理模式(自動切換)

使用 Gemini 3.0 Pro 免費額度最高 1M tokens (永遠推理模式)

使用 Grok 4 推理模式(自動切換)

---

How to publish a Claude artifact

How to share a ChatGPT link

How to share a Grok link

How to share Gemini Link

作業繳交規範

guidelines

Content share 作業繳交格式

• share only link, pure text, markdown (md)
• no attachments accepted, no html, screen dump, or png
• non-compliant homework will be rejected and returned to you

課堂練習 

Deadline: This Saturday at 23:59

Send all the share links to  me chang212@gmail.com by email with subject EX#8  [your id, your name]

 1.  Study Apple iPhone Architecture & Design Guides

(a) make LNA schematic (TSMC N7 製程的完整設計流程，包含完整元件表、元件值推導公式、die 面積估算) LNA=Low Noise Amplifier

(b) make LNA Die

share

(c) Build LNA Optimizer (SMITH Chart, S-parameters, Frequency Response), Merit of Figure (share)

share 1, share 2, share 3

(d) Build a Simplified (closed-form) LNA optimizer (with GD, A*) on Die, 3.5 GHz LNA TSMC N7. 

Note: LNA Optimizer with Die and sliders Synced  (Optimizer  with NM method added)

Prompts, Cont. Prompts (same as last)

(e) (選作) 需要付費版算力，免費版可能無法完成

Build an MNA model (Modified Nodal Analysis, as used in Cadence Spectre engine)  to optimize. Must verify your results to meet spec and parameters have to be realistic.

Want to get these figures, see the Claude share. (Opus 4.6)

Hints: all the prompts used 

prompts lined up

Supplemental

1. Explain Smith Chart

Electronics Example 8: Analog IC Design (OP741, diff pair, Parameter Optimization)

 BJT Differential Pair 

schematic with parameter optimizer

optimizer corrected

Common issues

2-stage diff pair (share from very simple diff pair), block diagram,  die, 

schematic (B&W), schematic (color)

corrected

Miller Compensation: miller slides,  slides detailed, 

Miller Compensation

OP 741

 schematic,  die, P&R

modern global placement: ePlace vs. RePlAce

 ePlace vs. RePlAce

compare ePlace with RePlAce animation

cell inflation

macros added (cell_w = 0.15)

final numbers

artifact

slides: modern global placement

Two-stage Cascode Class-AB RF PA driver: parameter optimization

  Two-stage Cascode Class-AB RF PA Driver targeting 5G n78 (3.5 GHz) in TSMC 28nm RF

Build Sub 6 GHz Power Amplifier Optimizer with Die Synced

share, artifact (Closed-Form)

2-stage RF PA driver 

Optimizer with Load-Pull Contours (analytical)

Optimizer with Load-Pull Contours (MNA mixed) share

Newton DC+ Multi-Harmonic Balance log

the design (2 by 2, 2 by 2 re-styled, Thermal model), log, ∠Γ_3f₀ phase (deg) · open=0, -170 deg

margin-first build, Thermal model

design choices

Two-stage Cascode Class-AB RF power amplifier: Placer

Placement of GaN on SiC 2 stage RF AMP

original , fixed (hardcoded), SA 1, QP, QP+SA (MNA, Small WireLen, non 0 viol.), 

• QP+SA with adaptive cooling schedule (2.55 WireLen, usual. 0 viol.) 
• add congestion penalty in energy (track overflow significantly reduced,  Bench, Overflow Comp, viz, detail viz)

QP+ILP+PrePass (No A* or SA, viol.) comparison with ACS  detail

Slides fit of SA for RF PA Layout

 Two-stage Cascode Class-AB RF power amplifier targeting 5G n78 (3.5 GHz) in TSMC 28nm RF

Placement (refinement of add congestion penalty in energy)

change log

Placement with style

benchmark

pipeline of placement process (comparison with ePlace, RePlAce)

RF Power Amp Driver TSMC N16FFC-RF

 RF Power Amp Driver TSMC N16FFC-RF (one stage)

 (Apple C1 by TSMA N4P is more advanced, no longer apply, not even N3E)

PA Lessons, PA Verified by computing the exact KCL residual at its converged solution, not because of blow up of MNA

Design Work Flow

Design matching network

Angelov model  (share)

PA revision with physical accuracy

what has been changed (shifting not chasing, good)

MNA

Optimizer Apply MNA

what has been changed surface, reality

artifact

artifact (slides)

Optimizer Apply Harmonic (close the loop)

change v9 MNA vs V21 Harmonic

Gemini 3.0 Pro

Opus 4.7 Adaptive

Apple C1 Doherty

v22

change documentation

visualization (pt A&B by tuning v22 2.2*Vdd, 2*Vdd too tight)

learning roadmap

v23 self-heating loop

v24 MNA for S parameters

v25* IMN+OMN, brute force+ NM Opti.

v26* IMN+OMN, brute force+ CMA-ES (v23-v26 change log)

block diagram artifact

RF PA driver with 10 dBm output, not PA itself (realistic spec, not just renaming)

TSMC N16FFC-RF revision (under construction)

PA Driver, Real C1 transceiver RF blocks on N4P

 TSMC N4P

artifact stacked-FET topologies

artifact

artifact

PA Driver, Real C1 transceiver RF blocks on N4P would be stacked-FET topologies on ~0.9 V core or 1.8 V I/O devices

EX#7 Mathematical Optimization

 Assignment Structure 作業架構

md version 

Deadline:  Next Saturday at 23:59 (one more week) 期中考緣故，順延一周

Send all the share links to  me chang212@gmail.com by email with subject EX#7 [your id, your name]

Students choose from three progressively harder assignments. Each builds on the interactive "Optimization in Hyperspace" 3D visualizer, which demonstrates five algorithms navigating a fitness landscape.

同學從三份難度遞增的作業中逐一完成。每份皆以互動式「超空間最佳化」3D 視覺化工具為基礎，展示五種演算法在適應度地形上的行為。

Problem 1 — Conceptual Understanding 概念理解

• Task 任務： Written reflection (300–500 words) on how each algorithm behaves on the landscape — local vs. global optima, exploration vs. exploitation.
• 撰寫心得（300–500字），描述各演算法在地形上的行為差異——區域最佳解 vs. 全域最佳解、探索 vs. 開發的取捨。
• Deliverable 繳交物： md (1–2 pages)
• Difficulty 難度： ★☆☆

Problem 2 — Mathematical Analysis 數學分析

• Task 任務： Implement gradient descent from scratch on a multimodal 2D function f(x,y) = sin(x)·cos(y) + 0.1(x² + y²). Test 3 starting points × 3 learning rates. Plot the surface + convergence paths.
• 自行實作梯度下降法，應用於多峰 2D 函數。測試 3 個起點 × 3 種學習率 (α = 0.01, 0.1, 0.5)，繪製曲面與收斂路徑。
• Deliverable 繳交物： Code + 1-page report in artifact
• Difficulty 難度： ★★☆

Problem 3 — Comparative Algorithm Design 演算法比較實驗

• Task 任務： Compare Gradient Descent vs. Simulated Annealing (exponential cooling T(t) = T₀·γᵗ). Run 50 trials each from random starts; vary T₀ and γ; produce success-rate table + plot.
• 比較梯度下降 vs. 模擬退火法（指數冷卻排程）。各執行 50 次隨機起點實驗，調整 T₀ 與 γ，製作成功率表格與圖表。
• Deliverable 繳交物： Code + 1–2 page analysis with table & plot in artifact
• Difficulty 難度： ★★★

---

Five Algorithms in the Visualizer 視覺化工具中的五種演算法

Algorithm 演算法	Type 類型	Key Trait 特性
Gradient Descent 梯度下降	Local 區域	Follows steepest slope; gets trapped in local optima 沿最陡方向走，易陷入區域最佳解
Nelder-Mead 單純形法	Local 區域	Derivative-free simplex; can stall near local optima 無需導數，但仍可能停在區域解
A* Search A*搜尋	Heuristic 啟發式	Graph-based, uses heuristic to guide search 圖形搜尋，以啟發函數引導
Simulated Annealing 模擬退火	Global 全域	Accepts worse moves probabilistically; escapes traps 以機率接受較差解，可跳脫陷阱
Global Optimization 全域最佳化	Global 全域	Systematic global search 系統性全域搜尋

---

Grading Notes 評分備註

• problem 1 is reflection-based — check for genuine engagement with the visualizer, not just generic definitions. HW1 為心得型——確認同學確實操作過視覺化工具，而非僅抄定義。
• problem 2, 3 require working code — verify plots are generated from their own implementation, not copied. HW2/HW3 需繳交可執行程式碼——確認圖表由自己實作產生。
• problem 3 requires statistical rigor (50 runs, multiple parameter settings). Check for proper experimental design. HW3 需具備統計嚴謹度（50次試驗、多組參數），檢查實驗設計是否完整。

RF PA IC Design Sub 6 GHz

Placement of GaN on SiC 2 stage RF AMP

original , fixed (hardcoded), SA 1, QP, QP+SA (MNA, Small WireLen, non 0 viol.), 

• QP+SA with adaptive cooling schedule (2.55 WireLen, usual. 0 viol.) 
• add congestion penalty in energy (track overflow significantly reduced,  Bench, Overflow Comp, viz, detail viz)

QP+ILP+PrePass (No A* or SA, viol.) comparison with ACS  detail

Slides fit of SA for RF PA Layout

 Two-stage Cascode Class-AB RF power amplifier targeting 5G n78 (3.5 GHz) in TSMC 28nm RF

Build Sub 6 GHz Power Amplifier Optimizer with Die Synced

Prompts, artifact (Closed-Form)

Optimizer with Load-Pull Contours (analytical)

Optimizer with Load-Pull Contours (MNA mixed) share

Placement (style)

benchmark

pipeline of placement process (comparison with ePlace, RePlAce)

ePlace vs. RePlAce

compare ePlace with RePlAce animation

cell inflation

macros added (cell_w = 0.15)

final numbers

artifact

slides: modern global placement

 RF Power Amp Driver TSMC N16FFC-RF (one stage)

 (Apple C1 by TSMA N4P is more advanced, no longer apply, not even N3E)

PA Lessons, PA Verified by computing the exact KCL residual at its converged solution, not because of blow up of MNA

Angelov model  (share)

PA revision with physical accuracy

what has been changed (shifting not chasing, good)

MNA

Optimizer Apply MNA

what has been changed surface, reality

artifact

artifact (slides)

Optimizer Apply Harmonic (close the loop)

change v9 MNA vs V21 Harmonic

Gemini 3.0 Pro

Opus 4.7 Adaptive

Apple C1 Doherty

v22

change documentation

visualization (pt A&B by tuning v22 2.2*Vdd, 2*Vdd too tight)

learning roadmap

block diagram artifact

RF PA driver with 10 dBm output, not PA itself (realistic spec, not just renaming)

TSMC N16FFC-RF revision (under construction)

TSMC N4P

artifact stacked-FET topologies

artifact

artifact

PA Driver, Real C1 transceiver RF blocks on N4P would be stacked-FET topologies on ~0.9 V core or 1.8 V I/O devices

slides wrap-up