EX#5 Placement and Routing for OP Amp IC

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P&R for OP 741.

schematic 

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Handout: Analog IC Design (OP741, diff pair, Placement & Routing)

1. Place and route the IC OP741

   Layout targets

   These targets apply only to the bonus phases. They are measured on the extended netlist from Phase 2 and averaged over the same 10 seeds. Phase 1 is graded on reproduction and ablation alone. "Phase 1 baseline" means your own reproduction of the handout on that netlist before any change.

   Metric	Target	Handout baseline
   Routing convergence	10/10 seeds with 0 shared cells	10/10 (core only)
   PathFinder rounds	mean ≤ 4	2–4
   Input path-length match	mean ≥ 95%, worst seed ≥ 90%	95.0% (seed 137)
   Input-net resistance mismatch, vias included	≤ 2%	—
   Coupling, each input net to VOUT	≤ 2 fF, and Vin+ within 10% of Vin−	—
   Output-stage centroid	within 1 cell of x = 40	—
   Output stage to input quad	≥ 40% of die height apart	—
   Thermal offset estimate (2 °C/mm model)	≤ 50 µV	—
   Wirelength + vias	≤ 1.15× Phase 1 baseline	434 + 24 (seed 137)
   Runtime per seed	≤ 2× Phase 1 baseline	—

   A team that misses a target but explains the trade-off with data can still earn most of the credit.

   Project tasks

   1. Run the handout's engine on the single-stage diff pair and the two-stage core. Reproduce every row of the handout's Table 1 and the two-stage result.
   2. Remove one part at a time and measure the effect on convergence, rounds, match, wirelength and vias:
      • SimPL-style anchors off
      • RUDY congestion stage off (λ = 0)
      • halo m = 0, 1 and 2
      • nets routed as trees vs split into two-pin connections
      • one layer vs three layers
   3. Record runtime per seed. This is the Phase 1 baseline used in the targets.

   Checkpoint: a reproduction table next to the handout's numbers, plus one ablation table. Explain any number that differs from the handout by more than 10%.

   
   
   
   
   Placer & Router for OP 741 (sample) 註：元件尺寸不對，可以使用Spice 計算驗證真正的幾何
   
   

   2.  Experiment with 10 seeds for the circuit in Problem 1

   Measure success, congestion, wirelength, overlap pairs (before/after), Vin length match. 
   
   
   
   

   
   

   

   benchmark